This invention relates to integrated circuits (xe2x80x9cICsxe2x80x9d), and more particularly to the internal structure of a P-channel, metal oxide semiconductor field effect transistor (xe2x80x9cMOSFETxe2x80x9d) that prevents undesired current flow through the transistor when the transistor forms part of an output buffer circuit connected to a bus.
Input/Output (xe2x80x9cI/Oxe2x80x9d) buffer circuits are in widespread usage in various applications. These buffers typically interface digital logic circuits with a common bus. The bus generally comprises a plurality of signal lines, e.g., data and address, connected to various circuit modules within a device such as a computer. In the alternative, the bus represents the external physical signal wires connected between the individual devices themselves (e.g., computer, printer, video screen, keyboard).
Referring to FIG. 1, a typical CMOS transistor buffer output circuit 100 generally comprises a P-channel MOSFET 104 and an N-channel MOSFET 108 connected in series between a positive voltage supply, Vdd, usually +3.0/+3.3 volts or +5.0 volts, and a negative voltage supply, Vss, generally at ground or zero volts. As such, the buffer 100 of FIG. 1 comprises the well-known, xe2x80x9cpush-pullxe2x80x9d, xe2x80x9cfull rail swingxe2x80x9d, CMOS output buffer circuit.
The gate terminal (G1, G2) of each transistor 104, 108 is connected to the digital and/or analog circuitry 112 that forms the remainder of the module circuitry. This module circuitry 112 can take on many different, known configurations, depending upon the application. The module circuitry 112 controls the switching of each transistor 104, 108 between its xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states. The drain terminals of the two transistors 104, 108 are connected together and to an I/O pad 116, which represents one signal line on a bus.
Typically, the module circuitry 112 controls the switching voltage applied to the gate terminals of the two output buffer transistors 104, 108 such that three different voltage conditions may exist on the I/O pad 116. One condition is where the P-channel transistor 104 is on and the N-channel transistor 108 is off, which switches the value of Vdd onto the bus. A second condition is where the N-channel transistor 108 is on and the P-channel transistor 104 is off, which switches the value of Vss, or zero volts, onto the bus. A third condition is a high impedance state where both transistors are off. In this state, the output buffer circuit 100 essentially disconnects the module circuitry 112 from the bus, and allows another module and its corresponding output buffer (not shown) to drive the bus. Generally, only one module can drive the bus at any one time. Otherwise, bus contentions could occur, possibly causing physical damage to circuit components connected to the bus.
Besides connecting the module circuitry 112 to the bus, the CMOS push-pull output buffer 100 of FIG. 1 performs other functions. One is to protect the electronic components of the module circuitry 112 from electrostatic discharge (xe2x80x9cESDxe2x80x9d). Static electric charge can build up on a person. When the person handles the electronic equipment, the built-up static charge can be transmitted as electrical current to the module circuitry 112. The charge can be potentially damaging to the electronic components of the module circuitry and to the power supply planes within the circuitry.
One common way of preventing the potentially damaging effects of electrostatic discharge is to provide protection against such discharge in the output buffer 100. Typically, this is done by scaling the N-channel and P-channel pull-up transistors 108, 104 to be of a relatively large size to reduce the resistance path encountered by the static charge between the I/O pad 116 and the Vss and Vdd power supply planes.
The geometries of IC devices continue to decrease in an effort to increase the number of devices (e.g., transistors, resistors, capacitors) integrated onto an IC substrate. Device sizes are now well within the sub-micron dimension range. Increases in integration have been achieved largely through advances in IC manufacturing techniques, such as photolithography.
With respect to CMOS transistors, the shrinking of device sizes has resulted in a lowering of the supply voltages used with these devices. For example, it has been known to predominantly use +5 V and ground as the power supply voltages within CMOS circuits. However, with increasingly smaller transistor sizes, the use of +5 volts presents problems in transistor operation. These problems include the hot electron carrier effect, which can degrade device performance. All of these problems result from the fact that an increasingly smaller physical device size must support the relatively high electric field provided for by the +5 volt power supply.
It is now common to use +3.0 V or +3.3 V as the value of the positive voltage supply for CMOS transistors. Use of this lower voltage alleviates the aforementioned problems with device operation caused by the +5 V power supply. It also results in significantly lower power dissipation per transistor, which is an important factor affecting such parameters as the overall operating speed of the IC.
However, the increasing prevalence of CMOS transistor circuits powered by the lower supply voltage of +3.0 V/+3.3 V has caused a problem when a plurality of modules or individual devices are connected together by a bus. Specifically, the problem occurs when an output buffer (such as the buffer 100 of FIG. 1) has its P-channel pull-up transistor connected to a Vdd of +3.0 V/+3.3 V, while another module driving the bus has placed a signal at +5 V onto the bus. This +5 V bus signal may originate from a module with internal CMOS circuitry operating at +5 V. When using the conventional CMOS push-pull circuit 100 of FIG. 1, the +5 V signal on the I/O pad 116 causes an undesired current to flow from the bus through the P-channel transistor 104 to Vdd. This current flow into the Vdd power supply plane can cause various problems, including damage to the module circuitry components connected to the plane and problems with the binary logic voltage levels on the bus. These components are xe2x80x9cback-poweredxe2x80x9d by the undesired current flow.
This undesired current can flow from the bus through the P-channel pull-up transistor 104 and into the Vdd power supply plane any time the voltage on the bus is greater than the voltage value of Vdd. As described above, one common example of this is when the voltage used by one module""s output buffer is lower than the voltage used by another module""s output buffer. Another common example occurs when it is desired to turn off all power to a module connected to the bus. The turned-off module is referred to as being xe2x80x9ccold sparedxe2x80x9d. The module is xe2x80x9ccoldxe2x80x9d and operating as a xe2x80x9csparexe2x80x9d since no power is applied. Often in fault tolerant systems, it is desired to cold spare unused circuits to reduce overall power consumption. The cold spare circuit must present a high impedance to the bus, to avoid any undesired current flowing from the bus into the Vdd power supply plane.
With respect to FIG. 1, when Vdd is equal to zero volts, the module circuitry 112 and associated output buffer 100 are cold. It is then desired to prevent any positive voltage values on the bus from providing a current through the P-channel transistor 104 to the Vdd power supply plane.
However, the output buffer circuit 100 is problematic in that the P-channel pull-up transistor 104 cannot prevent such current from flowing from the bus into the Vdd power supply plane. To see how this undesired current can flow, reference is made to FIG. 2. FIG. 2 is a cross-sectional illustration of the P-channel transistor 104 and N-channel transistor 108 of FIG. 1 formed in a Pxe2x88x92 silicon substrate 120. An Nxe2x88x92 well 124 is formed in the substrate 120. The drain and source of the P-channel transistor 104 are formed in the Nxe2x88x92 well 124. Both the drain 128 and source 132 of the P-channel transistor 104 comprise Pxe2x88x92 doped regions in the well 124. Also, a region 136 doped N+ is provided that functions as the well tap which connects to Vdd to charge up the well 124 during normal transistor operation. Similarly, the N-channel transistor 108 is formed directly in the Pxe2x88x92 substrate 120 by formation of a source 140 and a drain 144, both doped N+, together with a P+ well tie 148.
When a positive voltage is applied to the I/O pad 116 and when Vdd equals zero volts, current flows from the I/O pad 116 into the Nxe2x88x92 well 124 through the P+ drain 128. The P+ drain 128 and Nxe2x88x92 well 124 form a forward biased P/N junction diode. The current travels through the well 124 and to Vdd via the N+ well tap 136.
Another mechanism for undesired current flow through the P-channel transistor 104 occurs when the voltage on the gate terminal of the transistor is somewhat lower than the voltage on the I/O pad 116. As a result of this voltage differential, the P-channel transistor 104 will turn on and conduct current through the channel region 152. The channel 152 is that region of the Nxe2x88x92 well 124 located vertically underneath the oxide insulator separating the gate terminal from the substrate 120 and located laterally between the drain 128 and source 132. In this case, normal transistor operation is inverted in that now the drain 128 is acting as a source and the source 132 is acting as a drain.
The prior art has recognized the problem with undesired current flow through the P-channel transistor 104 functioning as the pull-up transistor in the CMOS output buffer circuit 100 of FIG. 1. The prior art contains a number of various schemes for preventing this undesired current flow. See, for example, U.S. Pat. Nos. 5,543,734, 5,387,826, 5,631,579, 5,444,397, 5,555,149, 5,565,794, 5,568,065, 5,629,634, 5,450,025 and 5,117,129. However, all of these patent references describe schemes that involve the use of additional, complex circuitry. This circuitry takes up valuable space on an IC substrate and requires additional IC processing steps. What is desired is a simpler, less complex method of preventing undesired current flow through the P-channel transistor that forms part of the CMOS output buffer circuit.
Objects of certain embodiments of the invention include the prevention of an undesired current flow from an external bus connected to an output buffer circuit containing a P-channel transistor and through that transistor to the positive voltage supply. Other objects include the prevention of this undesired current flow to the power supply plane of additional circuitry connected to the output buffer, thereby preventing back-powering of electronic components within the circuitry and also preventing any damage to such circuitry. Further objects include the prevention of the undesired current flow through the P-channel transistor in an output buffer circuit, thereby preventing problems with logic levels on the bus, such as degradation of the bus signals, bus latch-up or bus contention.
According to one aspect of the present invention, an output buffer circuit comprises a P-channel transistor and an N-channel transistor connected in series in a push-pull configuration. The N-channel transistor is formed in a Pxe2x88x92 substrate, while the P-channel transistor is formed in an Nxe2x88x92 well formed in the Pxe2x88x92 substrate. The N+ source of the N-channel transistor is connected to ground. The N+ drain of the N-channel transistor is connected to the P+ drain of the P-channel transistor and to the external bus. The P+ source of the P-channel transistor is connected to Vdd. Vdd is also connected to the Nxe2x88x92 well through a P+ well tie.
In operation, with Vdd equal to zero volts and a positive voltage on the bus (or anytime the bus voltage is greater than Vdd), current flows into the Nxe2x88x92 well through the forward biased junction diode comprising the P+ drain and the Nxe2x88x92 well. However, the current cannot continue into the power supply plane, since it is prevented from doing so by the two reverse biased PN junction diodes within the P-channel transistor, comprising the P+ source and Nxe2x88x92 well and the P+ well tie and Nxe2x88x92 well.
According to another aspect of the present invention, the P-channel transistor is formed in the Nxe2x88x92 well. That transistor has two separate well ties: the N+ well tie of the prior art and the P+ well tie of the first aspect of the present invention. Switch circuitry, external to the P-channel transistor, is provided to allow for the programmable connection of either one or both of the well ties to additional circuitry, depending upon the circuit configuration in which the P-channel transistor is utilized. This aspect of the present invention contemplates usage of the P-channel transistor and switch circuitry in a CMOS gate array.
The above and other objects and advantages of this invention will become readily apparent when the following description is read in conjunction with the accompanying drawings.